M6809E and Multiprocessing

[Derek Simmons]

My memory is quite foggy on this but I remember an article, maybe in
Byte magazine, about designing a multiprocessing using the MC6809E. I
think the hook of the article was that it made available the necessary
external timing signals to build a system with four processors and a
suggested application was for matrices. Does anybody else remember the
article(s) and happen to remember the magazine and the publication
date?

Thanks,
Derek

[Ira Baxter]

Post by Derek Simmons
My memory is quite foggy on this but I remember an article, maybe in
Byte magazine, about designing a multiprocessing using the MC6809E. I
think the hook of the article was that it made available the necessary
external timing signals to build a system with four processors and a
suggested application was for matrices. Does anybody else remember the
article(s) and happen to remember the magazine and the publication
date?

I don't remember this particular article.

But I worked on dual processor 6800, with each CPU using one phase
of the two-phase clock. This was for a GP "motherboard" that got
used in a variety of applications for TRW Credit back in the mid 70s
(we got some to the first prototype 6800s from Motorola...
no marking on the chips and several of the instructions didn't work bleah).
The most commercially visible application was the POS terminal for May
company,
that they rolled out across all of their stores in 1976.

The processors, the OS and the applications all understood the
dual-processor
nature of the system, and included real multiprocessor locks. The way
we used the system was to run the GP computations on one processor,
and dedicate I/O on the other one; as a consequence, we didn't need DMA.
The mag tape drive used to journal
POS transactions was implemented in software by serializing bits to
the tape head in real time at 50K bits per second.

The machine was actually pretty interesting.

[Dimiter Popoff]

Post by Ira Baxter
....
But I worked on dual processor 6800, with each CPU using one phase
of the two-phase clock.

Those were the days of synchronous bus 68xx, yeah... I never did
a dual CPU thing like the one you describe, but I did more than one
display controller sharing the framebuffer memory the same way.

Post by Ira Baxter
The mag tape drive used to journal
POS transactions was implemented in software by serializing bits to
the tape head in real time at 50K bits per second.

50 kbpS on a 1 MHz (?) 6800 must have been anything but easy to do,
especially reading from tape. You must have had your fun :-) .
What used to be popular (and really easy to do) back then was 300 bpS
Kansas City (I am sure you remember that as well). I did it also in
my first multi-task kernel, was a 6809 one, and managed to do it as a
separate task which took negligible CPU time, but I had a 6840 timer
and IIRC I used two if its sections.

Dimiter

------------------------------------------------------
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http://www.tgi-sci.com
------------------------------------------------------
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Original message: http://groups.google.com/group/comp.sys.m6809/msg/29d578e96592a0bc?dmode=source

[Dimiter Popoff]

Post by Ira Baxter
....
But I worked on dual processor 6800, with each CPU using one phase
of the two-phase clock.

Those were the days of synchronous bus 68xx, yeah... I never did
a dual CPU thing like the one you describe, but I did more than one
display controller sharing the framebuffer memory the same way.

Post by Ira Baxter
The mag tape drive used to journal
POS transactions was implemented in software by serializing bits to
the tape head in real time at 50K bits per second.

50 kbpS on a 1 MHz (?) 6800 must have been anything but easy to do,
especially reading from tape. You must have had your fun :-) .
What used to be popular (and really easy to do) back then was 300 bpS
Kansas City (I am sure you remember that as well). I did it also in
my first multi-task kernel, was a 6809 one, and managed to do it as a
separate task which took negligible CPU time, but I had a 6840 timer
and IIRC I used two if its sections.

Dimiter

------------------------------------------------------
Dimiter Popoff Transgalactic Instruments

http://www.tgi-sci.com
------------------------------------------------------
http://www.flickr.com/photos/didi_tgi/sets/72157600228621276/

Original message: http://groups.google.com/group/comp.sys.m6809/msg/29d578e96592a0bc?dmode=source

[Charles Richmond]

Post by Derek Simmons
My memory is quite foggy on this but I remember an article, maybe in
Byte magazine, about designing a multiprocessing using the MC6809E. I
think the hook of the article was that it made available the necessary
external timing signals to build a system with four processors and a
suggested application was for matrices. Does anybody else remember the
article(s) and happen to remember the magazine and the publication
date?

I remember a Circuit Cellar article in a BYTE magazine about
constructing a multi-processor system using Intel 8051's for
calculating values for displaying the Mandelbrot set fractal.

[Derek Simmons]

Post by Charles Richmond

Post by Derek Simmons
My memory is quite foggy on this but I remember an article, maybe in
Byte magazine, about designing a multiprocessing using the MC6809E. I
think the hook of the article was that it made available the necessary
external timing signals to build a system with four processors and a
suggested application was for matrices. Does anybody else remember the
article(s) and happen to remember the magazine and the publication
date?

I remember a Circuit Cellar article in a BYTE magazine about
constructing a multi-processor system using Intel 8051's for
calculating values for displaying the Mandelbrot set fractal.
--
+----------------------------------------------------------------+
|   Charles and Francis Richmond     richmond at plano dot net   |
+----------------------------------------------------------------+

Nope I’m not getting the two confused. The Mandelbrot engine built by
Steve was quite ingenious. I have a copy of that article someplace
too. It was issues October, November and December 1988.

The article I’m thinking of showed how to use the external clock and
control signals to build a shared memory system using four 6809E. I’m
beginning to wonder if I had read about it in Popular Electronics or
Radio & Electronics. I came across the article in college. The library
at RIT used to have a micro film area with pass issues of magazines
and news papers on micro film. I use to go up there between classes
and read the old articles of Byte, Popular Electronics and Radio &
Electronics.

After the July 4 I should have time to see if they still have the area
and pay them a visit. I just thought maybe somebody else could recall
having seen the article.

Derek

[Charles Richmond]

Post by Derek Simmons

Post by Charles Richmond

Post by Derek Simmons
My memory is quite foggy on this but I remember an article, maybe in
Byte magazine, about designing a multiprocessing using the MC6809E. I
think the hook of the article was that it made available the necessary
external timing signals to build a system with four processors and a
suggested application was for matrices. Does anybody else remember the
article(s) and happen to remember the magazine and the publication
date?

I remember a Circuit Cellar article in a BYTE magazine about
constructing a multi-processor system using Intel 8051's for
calculating values for displaying the Mandelbrot set fractal.
--
+----------------------------------------------------------------+
| Charles and Francis Richmond richmond at plano dot net |
+----------------------------------------------------------------+

Nope I’m not getting the two confused. The Mandelbrot engine built by
Steve was quite ingenious. I have a copy of that article someplace
too. It was issues October, November and December 1988.
The article I’m thinking of showed how to use the external clock and
control signals to build a shared memory system using four 6809E. I’m
beginning to wonder if I had read about it in Popular Electronics or
Radio & Electronics. I came across the article in college. The library
at RIT used to have a micro film area with pass issues of magazines
and news papers on micro film. I use to go up there between classes
and read the old articles of Byte, Popular Electronics and Radio &
Electronics.
After the July 4 I should have time to see if they still have the area
and pay them a visit. I just thought maybe somebody else could recall
having seen the article.

Okay, I found an article online that came from the May/June 1993
Computer Journal magazine, that delineated a multiprocessor 6809 system.
Perhaps this is what you were thinking of:

http://www.bradrodriguez.com/papers/6809cpu.htm

[lynchaj]

Post by Charles Richmond

Post by Derek Simmons

Post by Charles Richmond

Post by Derek Simmons
My memory is quite foggy on this but I remember an article, maybe in
Byte magazine, about designing a multiprocessing using the MC6809E. I
think the hook of the article was that it made available the necessary
external timing signals to build a system with four processors and a
suggested application was for matrices. Does anybody else remember the
article(s) and happen to remember the magazine and the publication
date?

I remember a Circuit Cellar article in a BYTE magazine about
constructing a multi-processor system using Intel 8051's for
calculating values for displaying the Mandelbrot set fractal.
--
+----------------------------------------------------------------+
|   Charles and Francis Richmond     richmond at plano dot net   |
+----------------------------------------------------------------+

Nope I’m not getting the two confused. The Mandelbrot engine built by
Steve was quite ingenious. I have a copy of that article someplace
too. It was issues October, November and December 1988.
The article I’m thinking of showed how to use the external clock and
control signals to build a shared memory system using four 6809E. I’m
beginning to wonder if I had read about it in Popular Electronics or
Radio & Electronics. I came across the article in college. The library
at RIT used to have a micro film area with pass issues of magazines
and news papers on micro film. I use to go up there between classes
and read the old articles of Byte, Popular Electronics and Radio &
Electronics.
After the July 4 I should have time to see if they still have the area
and pay them a visit. I just thought maybe somebody else could recall
having seen the article.

Okay, I found an article online that came from the May/June 1993
Computer Journal magazine, that delineated a multiprocessor 6809 system.
http://www.bradrodriguez.com/papers/6809cpu.htm
--
+----------------------------------------------------------------+
|   Charles and Francis Richmond     richmond at plano dot net   |
+----------------------------------------------------------------+

Hi! Thanks! The topic of 6809 multiprocessing is interesting. I
designed my N8VEM 6809 host processor so it appears as a peripheral
(8255 PPI) to the Z80 SBC CPU. That way the Z80 does all the IO
processing on the ECB and arbitrates access to peripherals. As a
result, builders can install as many 6809 host processors as they'd
like to operate in parallel.

Each 6809 has its own RAM/ROM for completely separate address space
from the Z80. The 6809 doesn't have much IO though, only a 6821 to
communicate with the Z80 but each also has a small mezzanine expansion
bus for custom IO. I am thinking these would make neat "smart
peripherals" like video boards with MC6845 or serial network
controllers. Some of the N8VEM builders are into remote monitoring
and wireless networking so a separate processor to handle networking
overhead is very attractive with the relatively slow Z80.

Thanks and have a nice day!

Andrew Lynch

[John Kent]

Post by lynchaj
Hi! Thanks! The topic of 6809 multiprocessing is interesting. I
designed my N8VEM 6809 host processor so it appears as a peripheral
(8255 PPI) to the Z80 SBC CPU. That way the Z80 does all the IO
processing on the ECB and arbitrates access to peripherals. As a
result, builders can install as many 6809 host processors as they'd
like to operate in parallel.
Each 6809 has its own RAM/ROM for completely separate address space
from the Z80. The 6809 doesn't have much IO though, only a 6821 to
communicate with the Z80 but each also has a small mezzanine expansion
bus for custom IO. I am thinking these would make neat "smart
peripherals" like video boards with MC6845 or serial network
controllers. Some of the N8VEM builders are into remote monitoring
and wireless networking so a separate processor to handle networking
overhead is very attractive with the relatively slow Z80.
Thanks and have a nice day!
Andrew Lynch

I was working on a Quad core 6809 in a XC3S1000 FPGA. It used internal
FPGA block RAM as cache. The FPGA 6809 core can run with an E clock at
up to 25 MHz (although the timing in the FPGA is marginal at that
speed). I got a bit stuck on the rotating priority of the bus
arbitration scheme. The cache was planned to be dual ported and partly
set associative with write through cache coherency between the processors.

Each CPU had it's own MMU (like the SWTPC) and I was going to
incorporate a 32 x 32 bit hardware multiplier register for each CPU
module. I had planned to implement it on an XESS XSA-3S1000 board, but
it would also be possible to use a Digilent XCS3S1000 Spartan 3 starter
board which sells for about US$150 last time I looked.

If anyone would like to continue to work on it they would be quite welcome.

http://members.optusnet.com.au/jekent/system09/index.html

The files are in the System09_2009-02-25.zip file in the System09/VHDL
folder. There is a unicpu and a quadcpu which uses 4 unicpus. I have not
worked on it since February 2009, so I'm not sure what state it's in.

John.